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<title>Signal Processing</title>
<link>http://hdl.handle.net/1983/1271</link>
<description/>
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<rdf:li rdf:resource="http://hdl.handle.net/1983/1645"/>
<rdf:li rdf:resource="http://hdl.handle.net/1983/1644"/>
<rdf:li rdf:resource="http://hdl.handle.net/1983/1576"/>
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<dc:date>2013-05-16T23:40:15Z</dc:date>
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<item rdf:about="http://hdl.handle.net/1983/1645">
<title>Communicating pictures: the test of future wireless networks</title>
<link>http://hdl.handle.net/1983/1645</link>
<description>Communicating pictures: the test of future wireless networks
Bull, DR
Before wireless multimedia applications can be truly successful, a number of technologically demanding problems must still be resolved. For example, future services will need to be delivered at a range of bit rates, dependent on network and channel characteristics, platform type, application and material content. End to end provision of multimedia information across network components of varying capability and performance will therefore impose the need for coding regimes which are inherently robust to different forms of loss and error. This paper addresses one of the most challenging coding problems- associated with the delivery of real time video over wireless communication networks. Specific examples will be based on H.264 transport over the 802.11 family of wireless LAN standards. The lecture will also describe how aspects of wireless video research in the University of Bristol have been successfully extracted from the laboratory and commercially exploited through a spin-out company, Provision Communications.
</description>
<dc:date>2007-02-01T00:00:00Z</dc:date>
</item>
<item rdf:about="http://hdl.handle.net/1983/1644">
<title>A novel lane feature extraction algorithm implemented on the TMS320DM6437 DSP platform</title>
<link>http://hdl.handle.net/1983/1644</link>
<description>A novel lane feature extraction algorithm implemented on the TMS320DM6437 DSP platform
Wang, Y; Dahnoun, N; Achim, AM
This paper presents an implementation of a novel lane edge feature extraction algorithm based on digital interpolation. The method is based on the observation that by zooming towards the vanishing point, the positions and the sizes of the lanes will not change significantly while other objects will. Comparing the zoomed image with the original image allows us to remove most of the unwanted features from the lane feature map. The proposed algorithm shows outstanding performance on extracting features belonging solely to the lanes embedded in severe noise environment. The algorithm runs in real-time on the TMS320DM6437 DSP platform from Texas Instruments. The system implemented can achieve at least 23 fps, without performing any code optimisation but only considering memory management.
</description>
<dc:date>2009-07-01T00:00:00Z</dc:date>
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<item rdf:about="http://hdl.handle.net/1983/1576">
<title>A toolset for the analysis and optimization of motion estimation algorithms and processors</title>
<link>http://hdl.handle.net/1983/1576</link>
<description>A toolset for the analysis and optimization of motion estimation algorithms and processors
Spiteri, T; Vafiadis, George; Nunez-Yanez, JL
This paper presents a reconfigurable processor designed to execute user-defined block-matching motion estimation algorithms, and a toolset for the design of such algorithms and for the configuration of the processor. The toolset enables the exploration of the processor's design space in order to find an optimal configuration depending on the target application. The use of the toolset to test different configurations for different kinds of video sequences is illustrated. Experimental results show the benefits and cost of certain optimizations in the motion estimation process, and that fast block-matching search algorithms can outperform full search algorithms commonly used in hardware implementations. The usefulness of the toolset in exploring the configuration space is also shown.
With accompanying conference presentation
</description>
<dc:date>2009-08-01T00:00:00Z</dc:date>
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<item rdf:about="http://hdl.handle.net/1983/1561">
<title>Run-time resource management in fault-tolerant network on reconfigurable chips</title>
<link>http://hdl.handle.net/1983/1561</link>
<description>Run-time resource management in fault-tolerant network on reconfigurable chips
Hosseinabady, M; Nunez-Yanez, JL
This paper investigates the challenges of run-time resource management in future coarse-grained network-on-reconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature expected in future processing systems which must support multiple applications whose processing requirements are not known at design time. This paper investigates a stochastic routing algorithm in a NoC-based system with dynamically reconfigurable tiles, able to cope with the dynamic behaviour of run-time task mapping. Experimental results show the efficiency of the proposed stochastic task mapping.
With accompanying conference poster
</description>
<dc:date>2009-08-01T00:00:00Z</dc:date>
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